Qg iNT + QSync: integrated subsystem for high precision clock solutions

Qg iNT & QSync is a set of hardware & software solutions delivering a full time sync capability for integration into systems that require precision sync capabilities.  Especially adapted to whitebox servers and systems being implemented for open specifications such as ORAN and OTII

Qg i QSync subsystem solution


  • 5G, ORAN, small cell clusters, C-RAN & neutral host equipment
  • Perfectly suited for any 5G S-plane configurations (LLS_C1 - LLS_C4) & different functional splits of RU/DU/CU in the RAN & edge evolution
  • OTII architecture sync implementations
  • Mobile edge computing platforms for enterprise, industrial IoT, datacenters etc.


  • Designed for rapid, scalable and easy integration
  • Adaptable, customize-able board design
  • High performance PTP clock
  • Algorithms for precision performance and ensembling resilience
  • Configurable, operates in multiple modes: PTP Grand Master, boundary & gateway clocks

The Qg iNT subsystem + QSync will support full GM (PRTC function) and telecom Boundary clock (T-BC).  Versions of this can be adapted for whitebox server DUs (Qg i), or switches (Qg iS) or radio units, RUs (Qg iR).

The Qg iNT enables flexible options for GNSS feed:

  1. Directly to Qg i, or
  2. Via the mother board with front panel SMA or
  3. From a dedicated GNSS receiver on mother board/NIC
  4. Via GNSS integrated NIC with SMA connector


Qg iNT detailed overview

Reserved pins on PCIe or software-defined Pins (SDPs) are available for the GNSS signals when not connected directly.   The Qg iNT has full suport for GPS, Beidou, Glonass, Galileo and QZSS.

Market Requirements

As 5G evolves from non standalone (NSA) supporting 4G today, to a standalone (SA) architecture with 5G NR, the support for massive MIMO radios, network slicing, low latency and tight synchronization are critical considerations. In order to meet phase and frequency requirements for applications in the 5G service based architecture, deploying more GMs (PRTC) at the edge is the optimal solution.  The low cost, small footprint Qg i along with the distributed QSync software can now be used to implement a flexible, sophisticated yet full turnkey PTP clock implementation in multiple network elements.

With virtualization and decomposition of 4G/5G base stations, the newly designed data-centers and CORDs (Central Office Re-architected as Data Centers) require a very high capacity, easily scalable PTP master (T-GM, T-BC) in providing synchronization to hundreds of PTP slave devices. Qgi + QSync combination is a rapid, simple way to integrate an industry leading technology to meet these challenges.

Next generation networks require this decentralized approach. The Assisted Partial Timing Support (APTS) architecture is designed for these networks and deliver precise phase and frequency to small cells in a scalable and cost-effective manner. Qg i + QSync is highly field-scalable solution and designed for such edge distributed architectures.

Some of the key disaggregated architectures are described by the Open RAN (ORAN) forum.

Product Summary

Qg i + QSync provides IEEE 1588-2008 (PTP) Grand Master and Boundary Clock functionality at low total cost of ownership, and comes with customization and integration services.  It leverages Qulsar’s unique  know how, experience and industry-leading technologies to deliver stringent timing for LTE-A, LTE-TDD, CBRS (USA), SxGP (Japan), private LTE and  5G architectures (both operator and private) and supports ITU-T G.8265 and G.8275 frequency and phase profiles. The product features multiple oscillator options to deliver a range of holdover performance.

The true innovation in this product lies in its "system-level" functionality, cost effectiveness and rapid integration in a fast moving market.



Whitebox sync subsystem imlementation

A general implementation appears above.  This is a powerful architecture, leveraging all the strengths of the "host processor" as well as the NICs in the system.  The Qg i + QSync implementation enable complete coordination of sync across the system.

Whitebox sync subsystem leveraging network interfaces the Intel Xeon

A more specific implementation (above) leverages the Xeon's network interface capabilities and strengths.  This too, is a complete sync system using the Qg i + QSync combination to implement a complete solution.

There could be other adaptations of the Qg i for RUs (leveraging a FPGA based processor, for example), with less functionality in the subsystem hardware (i.e. a Qg iR), or for a fronthaul sync aware switch, i.e. a Qg iS.

Recommended Process


ORAN architectures

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