In some ways a revival of the microcoded processor in a modern CMOS process with unprecedented resources, the C3 family *) sets new benchmarks in power efficiency and speed for specific applications. It is a field-reconfigurable system on a chip The new semantics are required to properly describe an architecture that is not quite like anything else in the contemporary neighborhood.
The C3 has on-chip an eighty-bit wide microprogram ROM and an eighty-bit wide microprogram RAM. If there were only the microprogram ROM on board and that was programmed once at the factory, by the designers, and never changed again, we would call the chip a traditional Complex Instruction Set processor, like an Intel X86 or Motorola 68000.
However, the on board microcode RAM permits field programmability. And of vital importance, it provides field programmability of operations that are an order of magnitude shorter in completion time than the instructions of the conventional Complex Instruction Set Computer.
Another way to execute operations that are an order of magnitude shorter in completion time than the instructions of the conventional Complex Instruction Set Computer (CISC), is to add external logic blocks to the CISC system. The added logic is nearly always application specific and if we choose to, we can make those external logic blocks field programmable.
Now we can see that micro-coding a CISC processor and adding logic to the periphery of a CISC processor has some type of equivalency. Both techniques allow application specific operations with short execution times to be executed under the control of a slower but general-purpose CISC processor. So Conemtech Field-Reprogrammable-Microcode actually equals external Logic. The microcode actually is used to replace external logic.
This is precisely the current legacy of Conemtech. Need a spare Ethernet Mac? Buy a MAC chip and stick it on the board, or program a MAC on an FPGA and stick that on the board, or microprogram a MAC in the microcode RAM. Which one is cheaper, lower power, more easily updated, or more quickly fixed in the field?
The answer to the question is application specific, of course. But the odds are good that for any specific application, the answer will be microcode, sometimes by very large multiples.
Conemtech has a variety of microcoded peripherals available ranging from TCP/IP accelerators to an Ethernet MAC, and Java acceleration. The equivalency of microcode and peripheral logic is well established at Conemtech. Need a slightly different MAC? Conemtech will code it, you can download it and install in the field, via the Internet, if that is what is needed. Need to switch to an 802.11n MAC? Swap it in when you need it, swap it out if you don’t.
Cache memory is another way to speed up special functions. So we can see that there is some equivalency between field reprogrammable microcode and cache. But in general, cache memory is much more expensive and power consuming than microcode memory. And RISC code, in particular, creates much more overhead data movement and power consumption does than application specific microcode.
Application specific microcoding works by allowing the meaning, the semantics, of CISC instructions to change when the task at hand changes. The control provided by the 80-bit wide microinstruction words allows prodigious amounts of efficient application-specific processing to be triggered by a single CISC instruction.
The impact of this level of control and this execution strategy on application specific operations is a general improvement in speed/power ratios over those of RISC processors. This improvement can be applied in whatever way is optimal for an application. The improvements in speed and power consumption are application specific. But in any specific application, the odds are that it will be significant, sometimes by very large multiples.
Caches accelerate processing in a generalized way but have several drawbacks. Their statistically controlled cache reload algorithms introduce unpredictable execution times making them inappropriate for real time operations. (The range of real time applications a processor can handle is determined by its worst-case execution times not the average case.) This makes RISC inappropriate for the networking operations that are now ubiquitous in many high volume markets.
RISC also requires that large amounts of inefficiently coded instructions be passed to the processor from memory. This produces power consumption numbers that ultimately cannot be compensated for with external logic or other power reduction techniques. The inefficiently coded instructions require large instruction caches and large expensive die areas for those caches.
All processors are in principle configurable at design time. The Conemtech C3 can be configured at any time, at design time, during manufacturing, and even in the field while in a product. As long as it is connected to a network, it can be configured in the feild without human being in the loop.
A microcode upgrade can include new functionality or a bug fix, including the repair of faulty instructions. Thus, products can be manufactured and deployed, and later retrofitted with new desired functions and even be repaired in the field.
RISC processor silicon areas are dominated by cache memories. Most memory traffic in a processor is caused by the instruction flow and not data. The instruction set architecture in C3 tends to have far higher information density. The benefits are that program sizes are many times smaller and less power is consumed in instruction transfers. RISC also lacks efficiency in doing bit and byte manipulation, signal processing and interpretation (e.g. Java byte-code).
Microcoding, unlike the use of caches, maintains real time operating characteristics, allowing the C3 to address applications that would normally require external logic or a complete external DSP. Thus the C3 can directly execute both general-purpose applications software and lower level baseband processing tasks without external components and complexity.
Conemtech has been creating microcoded systems for several years and maintains a library of microcoded "peripherals". Developers using the C3 can leverage this legacy and benefit from the re-configurable platform capabilities of the C3 to reduce development times, reduce power consumption and costs, and to benefit from a new level of field upgradeability in the networked age.
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